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low skew, 1-to-2, differential/lvcmos- to-0.7v hcsl fanout buffer ics85102i idt ? / ics ? 0.7v hcsl fanout buffer 1 ics85102agi rev. a june 10, 2008 g eneral d escription the ics85102i is a low skew, high performance 1- to-2 differential-to-hcsl fanout buffer and a mem- ber of the hiperclocks? family of high perfor- mance clock solutions from idt. the ics85102i has a differential clock input. the clk0, nclk0 input pair can accept most standard differential input levels. the clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics85102i ideal for those applications demanding well defined performance and repeatability. f eatures ? two 0.7v differential hcsl outputs ? selectable differential clk0, nclk0 or lvcmos inputs ? clk0, nclk0 pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? clk1 can accept the following input levels: lvcmos or lvttl ? maximum output frequency: 500mhz ? translates any single-ended input signal to 3.3v hcsl levels with resistor bias on nclk input ? output skew: 65ps (maximum) ? part-to-part skew: 600ps (maximum) ? propagation delay: 3.2ns (maximum) ? additive phase jitter, rms: 0.14ps typical @ 250mhz ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages b lock d iagram p in a ssignment hiperclocks? ic s ics85102i 16-lead tssop 4.4mm x 5.0mm x 0.925mm body package g package top view q0 nq0 q1 nq1 clk_en clk_sel iref clk1 clk0 nclk0 d le q 0 1 pulldown pulldown pulldown pullup pullup/pulldown 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clk_en clk_sel clk0 nclk0 clk1 nc nc iref gnd v dd q0 nq0 q1 nq1 v dd v dd
idt ? / ics ? 0.7v hcsl fanout buffer 2 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer t able 2. p in c haracteristics t able 1. p in d escriptions l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r e b m u ne m a ne p y tn o i t p i r c s e d 1n e _ k l ct u p n ip u l l u p . t u p n i k c o l c w o l l o f s t u p t u o k c o l c , h g i h n e h w . e l b a n e k c o l c g n i z i n o r h c n y s . h g i h d e c r o f e r a s t u p t u o x q n , w o l d e c r o f e r a s t u p t u o x q , w o l n e h w . s l e v e l e c a f r e t n i s o m c v l / l t t v l 2l e s _ k l ct u p n in w o d l l u p . t u p n i 1 k l c s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s t u p n i 0 k l c n , 0 k l c s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i s o m c v l / l t t v l 30 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 40 k l c nt u p n i / p u l l u p n w o d l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 51 k l cn w o d l l u p. s l e v e l e c a f r e t n i s o m c v l / l t t v l . t u p n i k c o l c d e d n e - e l g n i s 7 , 6c nd e s u n u. t c e n n o c o n 8f e r it u p n i 5 7 4 ( r o t s i s e r d e x i f l a n r e t x e n a a s e d i v o r p d n u o r g o t n i p s i h t m o r f ) . s t u p t u o k c o l c x q n / x q e d o m - t n e r r u c l a i t n e r e f f i d r o f d e s u t n e r r u c e c n e r e f e r 5 1 , 0 1 , 9v d d r e w o p. s n i p y l p p u s e v i t i s o p 2 1 , 1 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 4 1 , 3 10 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 6 1d n gr e w o p. d n u o r g y l p p u s r e w o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? 0.7v hcsl fanout buffer 3 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer t able 3a. c ontrol i nput f unction t able f igure 1. clk_en t iming d iagram enabled disabled nclk0 clk_en nq0, nq1 q0, q1 clk0 s t u p n is t u p t u o n e _ k l cl e s _ k l ce c r u o s d e t c e l e s1 q : 0 q1 q n : 0 q n 00 0 k l c n , 0 k l cw o l ; d e l b a s i dh g i h ; d e l b a s i d 01 1 k l cw o l ; d e l b a s i dh g i h ; d e l b a s i d 10 0 k l c n , 0 k l cd e l b a n ed e l b a n e 11 1 k l cd e l b a n ed e l b a n e . 1 e r u g i f n i n w o h s s a e g d e k c o l c t u p n i g n i l l a f a g n i w o l l o f d e l b a n e r o d e l b a s i d e r a s t u p t u o k c o l c e h t , s e h c t i w s n e _ k l c r e t f a
idt ? / ics ? 0.7v hcsl fanout buffer 4 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer t able 4b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v 10%, t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v dd = 3.3v 10%, t a = -40c to 85c t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v 10%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 7 9 . 23 . 33 6 . 3v i d d t n e r r u c y l p p u s r e w o pd e t a n i m r e t n u7 2a m note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 100.3c/w (0 mps) storage temperature, t stg -65c to 150c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h l e s _ k l c , 1 k l cv n i v = d d v 3 6 . 3 =0 5 1a n e _ k l cv n i v = d d v 3 6 . 3 =5a i l i t u p n i t n e r r u c w o l l e s _ k l c , 1 k l cv n i v , v 0 = d d v 3 6 . 3 =5 -a n e _ k l cv n i v , v 0 = d d v 3 6 . 3 =0 5 1 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i0 k l c n / 0 k l cv d d v = n i v 3 6 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i 0 k l cv d d v , v 3 6 . 3 = n i v 0 =5 -a 0 k l c nv d d v , v 3 6 . 3 = n i v 0 =0 5 1 -a v p p 1 e t o n ; e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 -v v : 1 e t o n l i . v 3 . 0 - n a h t s s e l e b t o n d l u o h s v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i .
idt ? / ics ? 0.7v hcsl fanout buffer 5 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer t able 5. ac c haracteristics , v dd = 3.3v 10%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 = l e s _ k l c0 0 5z h m 1 = l e s _ k l c0 5 2z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p 0 = l e s _ k l c0 . 22 . 3s n 1 = l e s _ k l c0 . 28 . 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 5 6s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 0 6s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r ) z h m 0 2 - z h k 2 1 ( z h m 0 0 12 2 . 0s p ) z h m 0 2 - z h k 2 1 ( z h m 0 5 24 1 . 0s p v x a m ; e g a t l o v t u p t u o m u m i x a m e t u l o s b a 0 1 , 5 e t o n 0 5 1 1v m v n i m ; e g a t l o v t u p t u o m u m i n i m e t u l o s b a 1 1 , 5 e t o n 0 0 3 -v m v b r 3 1 , 6 e t o n ; e g a t l o v k c a b g n i r 0 0 1 -0 0 1v t e l b a t s v e r o f e b e m i t b r 3 1 , 6 e t o n ; d e w o l l a s i0 0 5s p v s s o r c 9 , 8 , 5 e t o n ; e g a t l o v g n i s s o r c e t u l o s b a 0 5 20 5 5v m v s s o r c v f o n o i t a i r a v l a t o t s s o r c ; s e g d e l l a r e v o 2 1 , 8 , 5 e t o n 0 4 1v m 7 , 6 e t o n ; e t a r e g d e l l a f / e s i r n e e w t e b d e r u s a e m v m 0 5 1 + o t v m 0 5 1 - 6 . 05 . 5s n / v c d o4 1 e t o n ; e l c y c y t u d t u p t u o 5 45 5% t a d e r u s a e m s r e t e m a r a p l l a? z h m 0 5 2. e s i w r e h t o d e t o n s s e l n u v e h t m o r f d e r u s a e m : 1 e t o n d d . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t u p n i e h t f o 2 / t u p t u o e h t t a d e r u s a e m . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d h t i w d n a , e r u t a r e p m e t e m a s , e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n . m r o f e v a w d e d n e - e l g n i s m o r f n e k a t t n e m e r u s a e m : 5 e t o n . m r o f e v a w l a i t n e r e f f i d m o r f n e k a t t n e m e r u s a e m : 6 e t o n e b t s u m l a n g i s e h t . ) x q n s u n i m x q m o r f d e v i r e d ( m r o f e v a w l a i t n e r e f f i d e h t n o v m 0 5 1 + o t v m 0 5 1 - m o r f d e r u s a e m : 7 e t o n l a i t n e r e f f i d e h t n o d e r e t n e c s i w o d n i w t n e m e r u s a e m v m 0 0 3 e h t . e m i t l l a f d n a e s i r r o f n o i g e r t n e m e r u s a e m e h t h g u o r h t c i n o t o n o m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . g n i s s o r c o r e z . x q n f o e g d e g n i l l a f e h t s l a u q e x q f o e g d e g n i s i r e h t f o e u l a v e g a t l o v s u o e n a t n a t s n i e h t e r e h w t n i o p g n i s s o r c t a d e r u s a e m : 8 e t o n . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s l l a o t s r e f e r . g n i s s o r c s i e g d e h c i h w f o s s e l d r a g e r , t s e h g i h e h t o t t n i o p g n i s s o r c t s e w o l e h t m o r f n o i t a i r a v l a t o t e h t o t s r e f e r : 9 e t o n . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t n e m e r u s a e m s i h t r o f s t n i o p g n i s s o r c . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o o h s r e v o g n i d u l c n i e g a t l o v s u o e n a t n a t s n i m u m i x a m e h t s a d e n i f e d : 0 1 e t o n . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o o h s r e d n u g n i d u l c n i e g a t l o v s u o e n a t n a t s n i m u m i n i m e h t s a d e n i f e d : 1 1 e t o n e c n a i r a v d e w o l l a m u m i x a m e h t s i s i h t . x q n g n i l l a f d n a x q g n i s i r f o e g a t l o v g n i s s o r c l l a f o n o i t a i r a v l a t o t e h t s a d e n i f e d : 2 1 e t o n v e h t n i s s o r c . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . m e t s y s r a l u c i t r a p y n a r o f t . 3 1 : e t o n e l b a t s s e g d e g n i l l a f / g n i s i r r e t f a e g a t l o v l a i t n e r e f f i d v m 0 5 1 m u m i n i m a n i a t n i a m t s u m k c o l c l a i t n e r e f f i d e h t e m i t e h t s i v e h t o t n i k c a b p o o r d o t d e w o l l a s i t i e r o f e b b r . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . e g n a r l a i t n e r e f f i d v m 0 0 1 . % 0 5 e b t s u m e l c y c y t u d t u p n i : 4 1 e t o n
idt ? / ics ? 0.7v hcsl fanout buffer 6 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer a dditive p hase j itter additive phase jitter, integration range: 12khz - 20mhz at 250mhz = 0.14ps (typical) the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
idt ? / ics ? 0.7v hcsl fanout buffer 7 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer p arameter m easurement i nformation d ifferential i nput l evels hcsl o utput l oad ac t est c ircuit 475 iref 33 50 50 33 49.9 49.9 hcsl gnd 2pf 2pf qx nqx 0v 3.3v10% v dd hcsl o utput l oad ac t est c ircuit p art - to -p art s kew t sk(o) nqx qx nqy qy t sk(pp) nqx qx nqy qy part 1 part 2 v cmr cross points v pp gnd nclk0 v dd clk0 t pd o utput s kew (d ifferential i nput ) clk0 nclk0 q0:q3 nq0:nq3 t pd clk1 q0:q3 nq0:nq3 p ropagation d elay (d ifferential i nputs ) p ropagation d elay (lvcmos i nput ) 475 iref 50 50 hcsl gnd 0v scope 3.3v10% v dd d ifferential m easurement p oints for r ise /f all t ime q - nq -150mv +150mv 0.0v fall edge rate rise edge rate this load condition is used for i dd , t sk(o), t pd , and t jit measurements.
idt ? / ics ? 0.7v hcsl fanout buffer 8 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer p arameter m easurement i nformation , continued se m easurement p oints for d elta c ross p oint d ifferential m easurement p oints for d uty c ycle /p eriod d ifferential m easurement p oints for r ingback se m easurement p oints for a bsolute c ross p oint /s wing t stable v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v v rb t stable q - nq 0.0v clock period (differential) positive duty cycle (differential) negative duty cycle (differential) nq q v cross_max = 550mv v cross_min = 250mv v max = 1.15v v min = -0.30v q nq v cross_delta = 140mv
idt ? / ics ? 0.7v hcsl fanout buffer 9 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer a pplication i nformation f igure 2. s ingle e nded s ignal d riving d ifferential i nput figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_bias = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_bias in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_bias should be 1.25v and r2/r1 = 0.609. i nputs : clk i nput for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. clk/nclk i nputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : d ifferential o utputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. v_bias single ended clock input v dd clk nclk r1 1k c1 0.1u r2 1k
idt ? / ics ? 0.7v hcsl fanout buffer 10 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer f igure 3c. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 3a. h i p er c lock s clk/nclk i nput d riven by an idt o pen e mitter h i p er c lock s lvhstl d river examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3e. h i p er c lock s clk/nclk i nput d riven by a 3.3v hcsl d river zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 zo = 50 hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 f igure 3f. h i p er c lock s clk/nclk i nput d riven by a 2.5v sstl d river clk nclk hiperclocks sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
idt ? / ics ? 0.7v hcsl fanout buffer 11 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer r ecommended t ermination figure 4a is the recommended termination for applications which require the receiver and driver to be on a separate pcb. all traces should be 50 impedance. f igure 4a. r ecommended t ermination figure 4b is the recommended termination for applications which require a point to point connection and contain the driver f igure 4b. r ecommended t ermination and receiver on the same pcb. all traces should all be 50 impedance.
idt ? / ics ? 0.7v hcsl fanout buffer 12 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics85102i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85102i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 10% = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.63v * 27ma = 98.01mw ? power (outputs) max = 47.3mw/loaded output pair if all outputs are loaded, the total power is 2 * 47.3mw = 94.6mw total power _max (3.63v, with all outputs switching) = 98.01mw + 94.6mw = 192.61mw 2. junction temperature. junction temperature, tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 100.3c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.193w * 100.3c/w = 104.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 16-l ead tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w
idt ? / ics ? 0.7v hcsl fanout buffer 13 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 5. hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. the highest power dissipation occurs when v dd is high. power = (v dd_high ? v out ) * i out, since v out = i out * r l = (v dd_high ? i out * r l ) * i out = (3.63v ? 17ma * 50 ) * 17ma total power dissipation per output pair = 47.3mw f igure 5. hcsl d river c ircuit and t ermination v dd v out r l 50 ic ? i out = 17ma r ref = 475 1%
idt ? / ics ? 0.7v hcsl fanout buffer 14 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer r eliability i nformation t ransistor c ount the transistor count for ics85102i is: 614 t able 7. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (meter per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w p ackage o utline and d imensions p ackage o utline - g s uffix for 16 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? 0.7v hcsl fanout buffer 15 ics85102agi rev. a june 10, 2008 ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i g a 2 0 1 5 8i g a 2 0 1 5 8p o s s t d a e l 6 1e b u tc 5 8 o t c 0 4 - t i g a 2 0 1 5 8i g a 2 0 1 5 8p o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i g a 2 0 1 5 8l i a 2 0 1 5 8p o s s t " e e r f - d a e l " d a e l 6 1e b u tc 5 8 o t c 0 4 - t f l i g a 2 0 1 5 8l i a 2 0 1 5 8p o s s t " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 9. o rdering i nformation
ics85102i low skew, 1-to-2, differential/lvcmos-to-0.7v hcsl fanout buffer innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product spe cifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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